pl613- 01 1.8v to 3.3v, picopll , 3 -pll, 200mhz, 8 output clock ic micrel inc. ? 21 80 fortune drive ? san jose, ca 95131 ? usa ? t el +1 (408)944- 0800 ? f ax +1 (408)474-1000 ? www.micrel.com ? rev 06 /1 8/12 ? page 1 features ? designed for pcb space savings with 3 low-power programmable plls and up to 8 clock outputs. ? low -power consumption o 10 a typical when pdb is activated ? output frequency: o < 1 10 mhz @ 1.8v operation o < 166mhz @ 2.5v operation o < 200mhz @ 3.3v operation ? input frequency: o fundamental crystal: 10mhz to 40 mhz o reference input: 10 mhz to 200mhz ? programmable i/o pins can be configured as output enable (oe), configuration switching (csel), frequency switching (fselx), power down (pdb) inputs, or clock outputs. ? disabled outputs programmable as hiz or active low ? four distinct configurations selectable with csel[0 :1] ? single 1.8v, 2.5v, or 3.3v 10% power supply ? temperature range: 0 ? c to 70 ? c, - 40 ? c to +85 ? c ? available in green/rohs compliant 3x3 qfn or (t)ssop packages. description the pl613-01 is an advanced triple pll design based on picopll tm , worlds smallest programmable clock, technology. this advanced technology allows the 8 output pl613-01 to fit in to a small 3mmx3mm qfn package or (t)ssop for high performance, low- power, low-cost applications. besides its small fo rm factor and 8 outputs that can reduce overall system costs, the pl613-01 offers superior phase noise, ji tter and power consumption performance. the power down feature of pl613-01, when activated, allows the ic to consume less than 10a of power, while its csel[0:1] allows switching between up to 4 pre-programmed configurations. the fselx, on the other hand, allows frequency switching of tw o outputs (clk1 & clk2) on a single clock pin (clk2 ). block diagram programmable function xtal osc xout programmable pll1 xin/fin programmable pll3 clk4 odd/even divider (5-bits) clk5, oe6, csel0 clk6, oem, pdb clk7, oe0, csel1 vco1 vco3 clk0, fselx odd/even divider (5-bits) clk1, oe2 odd/even divider (5-bits) clk3, oe4 clk2 programmable pll2 vco2 fref fref ? 1, ? 2, ? 4, ? 8 odd/even divider (5-bits) odd/even divider (5-bits) fref fref programming interface output drive pdb fselx oe, oem ? 1, ? 2, ? 4, ? 8 ? 1, ? 2, ? 4, ? 8 csel[0:1] downloaded from: http:///
pl613- 01 1.8v to 3.3v, picopll , 3 -pll, 200mhz, 8 output clock ic micrel inc. ? 21 80 fortune drive ? san jose, ca 95131 ? usa ? t el +1 (408)944- 0800 ? f ax +1 (408)474-1000 ? www.micrel.com ? rev 06 /1 8/12 ? page 2 clk4 gnd clk2 clk3 , oe 4^ clk6 , oem^, pdb^ clk5 , oe 6^, csel0 vdd clk0, fselx^ vdd gnd clk1, oe2^ gnd xin, fin xout vdd 1 2 3 4 87 6 5 12 11 10 9 13 1415 16 clk7 , oe 0^, csel1 pin configuration ^ deno tes internal pull up qfn package (t)ssop package package pin assignment name package pin # type description qfn- 16l (t)ssop-16l clk0, fselx 1 7 b* - programmable clock (clk0) output or - clk2 frequency switching (fselx) input. gnd 3, 6, 12 2, 9, 12 p gnd connection. vdd 2, 9, 15 5, 8, 15 p vdd connection. clk1, oe2 4 10 b* - programmable clock (clk1) output or - output enable (oe) input for clk2. clk2 5 11 o programmable clock (clk2) output. clk3, oe4 7 13 b* - programmable clock (clk3) output or - output enable (oe) input for clk4. clk4 8 14 o programmable clock (clk4) output. xout 10 16 o crystal output pin. do not connect when using fin. xin, fin 11 1 i crystal or reference clock input. clk5, oe6 , csel0 13 3 b* - programmable clock (clk5) output or - output enable (oe) input for clk6 or - configuration switching input. clk6, oem, pdb 14 4 b* - programmable clock (clk6) output, or - output enable master (oem) for all clock outputs, o r - power down mode (pdb) input. clk7, oe0, csel1 16 6 b* - programmable clock (clk7) output or - output enable (oe) input for clk0 or - configuration switching input. * note : all bidirec tional buffers (i/os) incorporate an internal 60k? pull up resistor when used as an input except when pdb mode is used. in configurations that use pdb, the pdb pin will have a 10m? pull up resistor. 1 clk 4 gnd clk 2 clk 3 , oe 4^ clk 6 , oem ^, pdb ^ clk 5 , oe 6^, csel 0 vdd clk 0 , fselx vdd gnd clk 1 , oe 2^ gnd xin , fin xoutvdd clk 7 , oe 0^, csel 1 1615 14 13 12 11 10 9 8 7 6 5 4 3 2 downloaded from: http:///
pl613- 01 1.8v to 3.3v, picopll , 3 -pll, 200mhz, 8 output clock ic micrel inc. ? 21 80 fortune drive ? san jose, ca 95131 ? usa ? t el +1 (408)944- 0800 ? f ax +1 (408)474-1000 ? www.micrel.com ? rev 06 /1 8/12 ? page 3 key programming param eters clk[ 0:7 ] output frequency output drive strength programmable input/output clk[0,3,6] f vcox / (p*(1,2,4,8)), f ref or f ref / (p*(1,2,4,8)) clk[1,4, 7] f vco x / p clk[2,5] f vcox / p , f ref or f ref / p where f v co x = f ref * m / r m = 11 bit r = 8 bit p = 5 bit (odd/even divider) each output has three optional drive strengths to choose from. they are: ? low: 4ma ? std: 8ma (default) ? high:16ma most pins are multi-function i/os. in addition to clk, they can be configured to perform as: ? oe [0,2,4,6] C (output enable for individual i/os) ? oem C (master oe controlling all outputs) ? csel[0:1] C (device configuration switching) ? fselx C (clk2 frequency switching) ? pdb C (power down) ? clk[0:8] C (output) ? hiz or active low disabled state functional description the pl613- 01 is a highly featured, very flexible, advanced trip le pll design for high performance, low-power applications. the device accepts a low-cost fundam ental crystal input of 10mhz to 40 mhz or a reference clock input of 10 mhz to 200mhz and is capable of producing 8 distinct output fre quencies up to 200mhz. all 3-plls are fully programmable, with a total of five, 5-bit pos t vco, odd/even p -counter dividers with additional 1, 2, 4 or 8 p ost p-counter dividers to allow generating most demanding frequencies, ea sily. the outputs can b e programmed to deliver the generated frequencies fro m the plls, or the reference input. each bidirecti onal feature pin ( i/o ) on the pl613- 01 incorporates a 60k ? pull up resistor and can be configured to perform various functions. usage of various design features of these products is mentioned in the following paragraphs. pll programming the three plls in pl613- 01 are fully programmable. each pll is equipped with an 8-bit input frequency divider (r-counter) and an 11-bit vco frequency feedback loop (m-counter) divider. the three pll outputs are transferred to five 5-bit post vco , odd/even dividers (p-counter), as shown in the abov e diagrams. in addition, there are three optional ( 1, 2, 4 or 8) post p-counter dividers, that can fur ther divide the vco frequency. in general, the pll output frequency is determined by the following formula: f out = (f ref *m)/(r *p ) for output calculations, please note th at p includes the p counter bits plus the additional optional ( 1, 2, 4 or 8) dividers, if used. clkx (clock outputs) there are a maximum of 8 outputs available on the pl613- 01 . clock output frequencies can be configured as follows: clk[0,3,6] f vc ox / (p*(1, 2, 4, 8)) f ref (crystal or reference clock frequency) f ref / (p*(1,2,4,8)) clk[1, 7] f vcox / p clk[ 2, 4, 5] f vcox / p , f ref or f ref / p each output can be programmed with a 4ma, 8ma, or 16ma drive strength. the maximum output frequency is 200mhz @ 3.3v, 166mhz @ 2.5v or 110mhz @ 1.8v. downloaded from: http:///
pl613- 01 1.8v to 3.3v, picopll , 3 -pll, 200mhz, 8 output clock ic micrel inc. ? 21 80 fortune drive ? san jose, ca 95131 ? usa ? t el +1 (408)944- 0800 ? f ax +1 (408)474-1000 ? www.micrel.com ? rev 06 /1 8/12 ? page 4 oe (output enable) four pins can be configured as oe inputs for controlling individual clock outputs, as shown in t he table below: oex controls output on clk# oe0 clk0 oe2 clk2 oe4 clk4 oe6 clk6 note: typical enable time is < 500 ns plus one clock period. the oe feature can be programmed to allow the output to float (hi z), or to operate in the activ e low mode. the programming control for individual oes i s shown below: oe pin oe type (programmable) osc pl l output 0 0 (default) on on hi z 1 on on active 0 1 normal operation (default) oem (master output enable) one pin can be configured to be a single master oe (oem) input pin that controls all the outputs of th e pl613-01. in addition the state of the disabled outputs can be programmed to float (hi z) or to operate in the active low mode. the oem function operates on the following logic: oem pin oe type (programmable) osc pll output 0 0 (default) on on hi z 1 on on active 0 1 normal operation (default) note: typical enable time is < 500 ns plus one clock period. power-down control (pdb) when activated, pdb disables all the plls, the oscillator circuitry, counters, and all other activ e circuitry. pdb activation disables all outputs and the ic consumes <10a of power. the pdb input incorporates a 10 m ? pull up resistor for normal operating condition. the pdb feature can be programmed to allow the output to float (hi z), or to operate in the activ e low mode. the logic for pdb is shown below: pdb pin pdb type program osc pll output 0 0 (default) o ff off hi z 1 off off active 0 1 normal operation (default) note: typical enable time from power down is <2ms. on -the-fly configuration switching (csel) the pl613-01 can be programmed to allow switching between 4 different configurations, allowing f or changes in the output frequencies. many applicatio ns (i.e. video/audio) can use the same design footprin t, bu t allow for configuration switching, adhering to various standards. csel0 and csel1 are used in the switching selection. these pins incorporate a 60 k ? pull up resistor for normal operating condition. the logic for configuration switching of the programmed parts is shown below: csel1 csel0 programmed configuration 0 0 0 0 1 1 1 0 2 1 1 3 (default) note: typical enable time is <500s . on -the-fly output frequency switching between two output frequencies (fselx) the pl613-01 is equipped with the fselx feature to allow frequency switching of two frequencies on one of the output pins. frequencies assigned to clk1 and clk2 can be switched, when fselx is activated, on clk2 output. the logic for fselx is shown below: fselx clk2 output 0 frequency 2 1 (default) frequency 1 note: typical enable time is <10ns plus one clock p eriod . downloaded from: http:///
pl613- 01 1.8v to 3.3v, picopll , 3 -pll, 200mhz, 8 output clock ic micrel inc. ? 21 80 fortune drive ? san jose, ca 95131 ? usa ? t el +1 (408)944- 0800 ? f ax +1 (408)474-1000 ? www.micrel.com ? rev 06 /1 8/12 ? page 5 layout recommendations the following guidelines are to assist you with a p erformance optimized pcb design: signal integrity and termination considerations - keep traces short! - trace = inductor. with a capacitive load this equals ringing! - long trace = transmission line. without proper termination this will cause reflections (looks like ringing). - design long traces (> 1 inch) as striplines or microstrips with defined impedance. - match trace at one side to avoid reflections bouncing back and forth. decoupling and power supply considerations - place decoupling capacitors as close as possible to the v dd pin(s) to limit noise from the power supply - multiple v dd pins should be decoupled separately for best performance. - addition of resistors in series with v dd can help prevent noise from other board sources. traditionally ferrite beads are also used for this purpose but with the pl613-01 the results are bette r when using resistors. typical cmos termination place series resistor as close as possible to cmos output cmos output buffer (typical buffer impedance 20 ) to cmos input series resistor use value to match output buffer impedance to 50 trace. typical value 30 50 line crystal tuning circuit series and parallel capacitors used to fine tune the crystal load to the circuit load. cst C series capacitor , used to lower circuit load to match crystal load . raises frequency offset . this can be eliminated by using a crystal with a cload of equal or greater value than the oscillator. cpt C parallel capacitors , used to raise the circuit load to match the crystal load . lowers frequency offset. crystal xin 1 8 xout cpt cpt cst downloaded from: http:///
pl613- 01 1.8v to 3.3v, picopll , 3 -pll, 200mhz, 8 output clock ic micrel inc. ? 21 80 fortune drive ? san jose, ca 95131 ? usa ? t el +1 (408)944- 0800 ? f ax +1 (408)474-1000 ? www.micrel.com ? rev 06 /1 8/12 ? page 6 layout exam ple u1 = pl613-01 in qfn-16l. in this example all 8 ou tputs are used. c1a, c2a, c3a = 0.1f and c1b, c2b, c3b = 1f for p ower supply decoupling. the vias connected to the capacitors go to the ground plane inside the pcb. r1p, r2p, r3p = 10 ? for power supply filtering. the power supply filt er is a 1 st order low pass filter wit h -3db at 30khz. it is important that the frequencies of the loop bandwidth of the plls are filtered properly. the loop bandwidth of the plls is in the range 100khz to 1mh z, depending upon the programmed configuration. the vias connected to rp1, rp2 and rp3 go to the vdd plane i nside the pcb. r0 ~ r7 = 30 ? for matching clk0 ~ clk7 outputs to the pcb trace impedance. place the resistors as close as possible to the ic pins and design the traces to th e target clock inputs as transmission lines (micros trip or stripline) for the best signal integrity and the l o west emi. when using ferrite beads instead of rp1, rp2 or rp2 , make sure the resonance frequency of the bead wit h the decoupling capacitors is below 50khz, to not interf ere with the pll loop bandwidth. this requirement i s difficult to fulfill so we recommend using the resistors rp1, rp 2 and rp3 for power supply filtering. clk4 clk3 clk2 clk5 clk6 clk7 clk0 clk1 downloaded from: http:///
pl613- 01 1.8v to 3.3v, picopll , 3 -pll, 200mhz, 8 output clock ic micrel inc. ? 21 80 fortune drive ? san jose, ca 95131 ? usa ? t el +1 (408)944- 0800 ? f ax +1 (408)474-1000 ? www.micrel.com ? rev 06 /1 8/12 ? page 7 electrical specifications absolute maximum ratings parameters symbol min. max. units supply voltage range v dd -0.5 4.6 v input voltage range v i -0.5 v dd +0.5 v output voltage range v o -0.5 v dd +0.5 v soldering temperature (green package) 260 ? c data retention @ 85 ? c 10 year storage temperature t s - 65 150 ? c ambient operating temperature* - 40 85 ? c exposure of the device under conditions beyond the limits specified by maximum ratings for extended pe riods may cause permanent damage to the device and affect product reliability. these conditions r epresent a stress rating only, and functional opera tions of the device at these or any other condition s above the operational limits noted in this specification is not implied. *operating temperature is guaranteed by design. par ts are tested to commercial grade only. ac specifications parameters conditions min. typ. max. units crystal input frequency (xin) fundamental crystal 10 40 mh z input (fin) frequency @ v dd = 3.3v, 10% 10 200 mhz @ v dd = 2.5v, 10% 166 @ v dd = 1.8v, 10% 110 input (fin) signal amplitude internally ac coupled 0. 8 v dd vpp output frequency @ v dd = 3.3v, 10% (high drive) 1 200 mhz @ v dd = 2.5v, 10% (high drive) 166 @ v dd = 1.8v, 10% (high drive) 110 settling time at power-up (v dd > 90% of operating v dd ) 2 ms output enable time oe function; ta=25o c, 15pf load. add one clock period to this measurement for a usable clock output. 500 ns pdb function; ta=25o c, 15pf load 2 ms v dd sensitivity frequency vs. v dd , 10% -2 2 ppm output rise time 15pf load, 10/90% v dd , high drive, 3.3v 1.2 1.7 ns output fall time 15pf load, 90/10% v dd , high drive, 3.3v 1.2 1.7 ns duty cycle pll driven output, @ v dd /2, 15pf l oad , high drive, over entire frequency range 45 50 55 % period jitter* (10,000 samples) configuration dependant, with capacitive decoupling between v dd and gnd. 300 ps * note: jitter perform ance depends on the programm i ng parameters. downloaded from: http:///
pl613- 01 1.8v to 3.3v, picopll , 3 -pll, 200mhz, 8 output clock ic micrel inc. ? 21 80 fortune drive ? san jose, ca 95131 ? usa ? t el +1 (408)944- 0800 ? f ax +1 (408)474-1000 ? www.micrel.com ? rev 06 /1 8/12 ? page 8 dc specifications parameters symbol conditions min. typ. max. units supply current , v dd = 3.3v i dd all 8 outputs @ 20mhz no load , v dd = 3.3v 17 23 ma supply current, v dd = 2.5v i dd all 8 outputs @ 20mhz no load , v dd = 2.5v 13.5 18 ma supply current, v dd = 1.8v i dd all 8 outputs @ 20mhz no load, v dd = 1.8v 9 .5 13 ma supply current i dd when pdb=0 10 a operating voltage v dd configured for 3.3v operation 2.97 3.3 3.63 v configured for 2.5v operation 2.25 2.5 2.75 configured for 1.8v operation 1.62 1.8 1.98 output low voltage v ol i ol = +4ma std drive, 3.3v 0.4 v output high voltage v oh i oh = -4ma std drive, 3.3v 2.4 v output current, low drive i osd v ol = 0.4v, v oh = 2.4v, 3.3v 4 ma output current, std drive i osd v ol = 0.4v, v oh = 2.4v, 3.3v 8 ma output current, high drive i ohd v ol = 0.4v, v oh = 2.4v, 3.3v 16 ma crystal specifications parameters symbol min typ max units fundamental crystal resonator frequency f xin 10 40 mhz crystal loading rating c l (x ta l) 15 pf operating drive level 0.1 2 mw metal can crystal shunt capacitance c0 5.5 pf esr max esr 40 ? small smd crystal shunt capacitance c0 2.5 pf esr max esr 60 ? downloaded from: http:///
pl613- 01 1.8v to 3.3v, picopll , 3 -pll, 200mhz, 8 output clock ic micrel inc. ? 21 80 fortune drive ? san jose, ca 95131 ? usa ? t el +1 (408)944- 0800 ? f ax +1 (408)474-1000 ? www.micrel.com ? rev 06 /1 8/12 ? page 9 package drawings (green package com pliant) qfn- 16l tssop- 16l ssop- 16l symbol dimension in mm min. max. a 0. 7 0.8 a1 0.05 0. 05 a3 0.20 b 0. 18 0. 30 d 3.00 bsc e 3.00 bsc d1 -- 1. 70 e1 -- 1.70 l 0.30 0.50 e 0.50 bsc symbol dimension in mm min. max. a - 1.20 a1 0.05 0.15 b 0.19 0.30 c 0. 09 0.20 d 4.90 5. 10 e 4.30 4.50 h 6.20 6.60 l 0.45 0.75 e 0.65 bsc symbol dimension in mm min. max. a 1.35 1.75 a1 0.05 0.15 b 0. 20 0.30 c 0.18 0.25 d 4.80 5.00 e 3.80 3.98 h 5.80 6.20 l 0. 40 1.27 e 0.635 bsc c l a e h d a1 e b ? seating plane a1 a3 b e1 d1 a e l d e pin 1 dot c l a e h d a1 e b downloaded from: http:///
pl613- 01 1.8v to 3.3v, picopll , 3 -pll, 200mhz, 8 output clock ic micrel inc. ? 21 80 fortune drive ? san jose, ca 95131 ? usa ? t el +1 (408)944- 0800 ? f ax +1 (408)474-1000 ? www.micrel.com ? rev 06 /1 8/12 ? page 10 ordering inform ation (green package com pliant) for part ordering, please contact our sales departmen t: 2180 fortune drive, san jose, ca 95131, usa tel: (408) 944-0800 fax: (408) 474-1000 part number the order number for this device is a combination of the following: part number, package type and operating temperature range pl 613- 01- xx x x x x * micrel will assign a unique 3-digit id code for eac h approved programmed part number. part number/order number marking ? package option pl613- 01 - xxx oc p613- 01 xxx (i) lllll 16 -pin tssop (tube) pl613- 01 - xxx oc -r p613- 01 xxx (i) lllll 16 -pin tssop (tape and reel) pl613- 01 - xxx qc -r p61301 xxx (i) lll 16 -pin qfn (tape and reel) pl613- 01 - xxx xc p613- 01 xxx (i) lllll 16 -pin ssop (tube) pl613- 01 - xxxxc -r p613- 01 xxx (i) lllll 16 -pin ssop (tape and reel) ? marking notes : 1) the i after the three digit programming code will be mark ed for industrial temperature grade products only. commercial grade products will not have a character in this po sition. 2) lll represents the pro duction lot number micrel inc., reserves the right to make changes in its products or specifications, or both at any time without notice. the in formation furnished by micrel is believed to be accurate and reliable. however, micrel makes no guarantee or w arranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : micrels products are not authorized for use as c ritic al components in life support devices or systems wi thout the express written approval of the president of micrel inc. part number temperature c=commercial (0 ? c to 70 ? c) i= industrial (- 40 ? c to +85 ? c) package type o=tssop- 16l q=qfn- 16l x= ssop- 16l 3 digit id code * (will be assigned at programming time) none= tube r=tape and reel downloaded from: http:///
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